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Freescale Semiconductor Advance Information
Document Number: MC33902 Rev. 3.0, 8/2009
High Speed CAN Interface with Embedded 5.0 V Supply
The MC33902 is a high speed CAN physical interface. The device includes an internal 5.0 V supply for the CAN bus transceiver, and requires only a connection to a battery line. The MC33902 provides 4 operation modes, including low power modes with remote and local wake-up. The device has very low sleep and standby current consumption. Features * High speed CAN interface for baud rates of 40 kb/s to 1.0 Mb/s * Compatible to ISO11898 standard * Single supply from battery. No need for a 5.0 V supply for CAN interface * I/O compatible from 2.75 V to 5.5 V via a dedicated input terminal (3.3 V or 5.0 V logic compatible) * Low Power mode with remote CAN wake-up and local wake-up recognition and reporting * CAN bus failure diagnostics and TXD/RXD pin monitoring, cold start detection, wake-up sources reported through the ERR pin * Enhanced diagnostics for bus, TXD, RXD and supply pins available through Pseudo SPI via existing terminals EN, STBY and ERR. * Split terminal for bus recessive level stabilization * INH output to control external voltage regulator * Pb-free packaging designated by suffix code EF
33902
HIGH SPEED CAN PHYSICAL INTERFACE
EF SUFFIX (PB-FREE) 98ASB42565B 14-PIN SOICN
ORDERING INFORMATION
Device MCZ33902EF/R2 Temperature Range (TA) -40C to 125C Package 14 SOIC
VBAT
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Voltage Regulator INH WAKE INH VIO VDD VDD I/O STBY EN ERR CAN Controller Tx Rx TXD RXD I/O & Control Bus Diag. CANH SPLIT Bus Driver & Receiver CANL VSUP GND 5V Reg
MCU
30 CAN bus 30
Figure 1. MC33902 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007-2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
INH
Detector VSUP 5.0 V Regulator
INH
control VSUP Wake-up Receiver
WAKE
Monitoring VIO Vio TXD
Pattern Detection
Driver RXD 2.5 V Rin
QH CANH
Logic Control / Interface / P_SPI
EN
Differential Receiver Rin Thermal CANL
STBY
Driver
QL
ERR
VDD Failure Detection Buffer SPLIT
GND
& Management
Figure 2. 33902 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
PIN CONFIGURATION
TXD GND VDD RXD VIO EN INH
1 2 3 4 5 6 7 14 13 12 11 10 9 8
STBY CANH CANL SPLIT VSUP WAKE ERR
Figure 3. 33902 Pin Connections Table 1. 33902 Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Name TXD GND VDD RXD VIO EN INH ERR WAKE VSUP SPLIT CANL CANH STBY
Pin Function Input Output Output Output Input Input Output Output Input Input Output Input/output Input/output Input
Formal Name Transmit data Ground Voltage Digital Drain Receive data Voltage supply for I/O Enable Inhibit Active low Error Wake Voltage supply Split CAN LOW CAN HIGH Standby
Definition CAN bus transmit data input pin Ground termination CAN dedicated internal voltage regulator, (decoupling capacitor required for voltage stabilization) CAN bus receive data output pin, wake-up flag in Low Power mode Input supply for the digital input output pins Enable input for device static mode control. MOSI (Master Out, Slave In) during P_SPI operation. Inhibit output for control of an external power supply regulator Pin for static error and wake-up flag reporting MISO (Master In, Slave Out) during P_SPI operation. Wake input Battery supply pin Output for connection of the CAN bus termination middle point CAN low pin CAN high pin Standby input for device static mode control. CLK (Clock) during P_SPI operation.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS DC voltage on VSUP DC voltage on CANL, CANH, SPLIT Continuous (Steady State) Transient Voltage (Load Dump) DC voltage on VIO DC voltage on EN, STBY, ERR, TXD, RXD DC voltage on Wake Continuous current on CANH and CANL DC current on VDD ESD on CANH, CANL and Split (HBM) ESD on CANH, CANL and Split (IEC61000-4, CZAP = 150 pF, Rzap = 330 ) ESD on all pins except CANH, CANL, Split (HBM) THERMAL RATINGS Junction temperature Ambient temperature Storage temperature THERMAL RESISTANCE Thermal resistance junction to ambient (SO14) RJA 140 C/W TJ TA TST 150 -40 to 125 -55 to 165 C C C VVIO VDIG VWAKE ILH IVDD VESDCH VESDIEC VESCH VSUP VBUS -27 to +27 -27 to +40 -0.3 to 5.5 -0.3 to VIO +0.3 -0.3 to 29 200 240 +-2000 +-8000 +-2000 V V V mA mA V V V -0.3 to +40 V V Symbol Value Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 27 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic INPUT PIN (VSUP) Nominal voltage range Extended voltage range, fully functional, parametric value(s) not guaranteed Supply current in Sleep mode, VSUP 13.5 V, VIO = 0 V Supply current in Standby mode (VSUP 13.5 V, 5 V enabled at VDD terminal, default operation) Supply current in Normal mode, TXD high Supply current in Listen Only mode, TXD high BATFAIL Flag internal threshold BATFAIL Flag hysteresis VSUP under-voltage threshold (In Normal and Listen only) VSUP under-voltage threshold hysteresis (In Normal and Listen only) OUTPUT PIN (VDD) Output Voltage Drop voltage at IOUT = 100 mA VDD low detection threshold Output Current Capability, for information only. Current for CAN tranceiver supply only. Current Source Capability, in standby and Go To Sleep mode. Thermal prewarning junction temperature (Available via P_SPI. ERR low if ERR-EXT flag is set) Thermal shutdown (junction) Temperature threshold difference External Capacitor INPUT SUPPLY PIN (VIO) Voltage range Input Current in Normal and Listen Only modes, RXD and ERR PIN current =0, TXD = high Input Current in Normal mode, TXD = 0 V (Normal and Listen Only) Input Current in Standby or Sleep mode, VIO < 5.0 V VIO IVIOLIST IVIONORM IVIOSLP-STBY 2.75 5.0 50 - - 30 350 2.0 5.5 200 1000 5.0 V A A A VDDOUT VDROP VDDTH IOUT IOUTLP TPR TSD TDIFF CEXT 4.5 4.0 150 5.0 130 155 20 1.0 5.0 4.25 150 170 5.5 500 4.5 100 170 190 100 V mV V mA A C C C F VSUPN VSUPEX ISUPSLEEP ISUPSTB ISUPNORMAL ISUPLISTEN VBFTHS VBFHYS VSUV VSUVHYS 5.5 4.5 1.0 1.0 1.5 10 14 4.0 4.0 3.3 0.5 5.8 0.2 30 6.0 6.0 5.5 27 5.5 V V A A mA mA V V V V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 27 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic LOGIC INPUT PINS (EN, STBY, TXD) High Level Input Voltage Low Level Input Voltage Pull-down Current, EN, STBY, VIN = VIO Pull-up Current, TXD, VIN = 0 V DATA OUTPUT PINS (RXD) AND (ERR) Low Level Output Voltage I = 5.0 mA High Level Output Voltage I = -3.0 mA High Level Output Current V = VIO - 0.4 V Low Level Output Current V = 0.4 V OUTPUT PIN (INH) Output Drop Voltage (IINH), IOUT = 100 uA) leakage Current (Sleep mode) INPUT PIN (WAKE) Low level threshold voltage High level threshold voltage Input Current VWAKE = -0.2 to 18 V LOGIC INPUT/OUTPUT PINS (CANH, CANL) Bus pins common mode voltage for full functionality Differential input voltage, recessive state at RXD Differential input voltage, dominant state at RXD Differential input hysteresis (RXD) Input resistance Differential input resistance Common mode input resistance matching CANH output voltage(45 < RBUS < 65 ) TX dominant state TX recessive state CANL output voltage(45 < RBUS < 65 ) TX dominant state TX recessive state Differential output voltage(45 < RBUS < 65 ) TX dominant state TX recessive state 33902 VOH-VOL 1.5 -500 2.0 0.0 3.0 50 V mV VCANL 0.5 2.0 1.5 2.5 2.25 3.0 VCOM VCANH-VCANL-R VCANH-VCANL-D VDIFF-HYST RIN RIND RINM VCANH 2.75 2.0 3.5 2.5 4.5 3.0 V -12 900 5.0 10 -3.0 100 0.0 50 100 3.0 12 500 V mV mV mV k k % V WAKELTH WAKEHTH IWAKEIN 2.0 2.0 -10 2.5 2.7 0 3.0 3.5 10 V V A INHDROP INHLEAK 0.05 0.2 0.8 5.0 V A IOUTLOW 2.0 5.0 12 mA IOUTHIGH -12 -5.0 -2.0 mA VOUTHIGH 0.7 VIO VIO V VOUTLOW 0.0 0.3 VIO V VIH VIL IPD EN-STBY IPD TXD 0.7 VIO 1.0 4.0 -250 0.3 VIO 10 V V A A Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 27 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic LOGIC INPUT/OUTPUT PINS (CANH, CANL) (CONTINUED) CANH output current capability - Dominant state CANL output current capability - Dominant state CANL over-current detection - Error reported in register CANH over-current detection - Error reported in register CANH, CANL input resistance device supplied and in Sleep mode, VCANH, VCANL from 0 V to 5.0 V CANL, CANH output voltage in Sleep and Standby modes (45 < RBUS < 65 ) CANH, CANL input current, device un supplied, VSUP and VIO connected to GND (ref. fig.) VCANH, VCANL = 5.0 V VCANH, VCANL = -2.0 to + 7.0 V CANH AND CANL DIAGNOSTIC INFORMATION CANL to GND detection threshold CANH to GND detection threshold CANL to VBAT detection threshold, valid if VSUP > 7.0 V CANH to VBAT detection threshold, valid if VSUP > 7.0 V CANL to VDD detection threshold CANH to VDD detection threshold SPLIT Output voltage Loaded condition Isplit =+- 500 A Unloaded condition Rmeasure > 1.0 M Leakage current -12 V < VSPLIT< +12 V -22 V < VSPLIT< +35 V ILSPLIT 0.0 5.0 70 VSPLIT 0.3 VDD 0.45 VDD 0.5 VDD 0.5 VDD 0.7 VDD 0.55 VDD A V VLG VHG VLVB VHVB VL5 VH5 1.75 1.75 VSUP-2.0 VSUP-2.0 VDD-0.43 VDD-0.43 V V V V V V ICAN 250 400 A ICANH ICANL ICANL-OC ICANH-OC RINSLEEP VCANLP 25 75 -195 5.0 -0.1 120 -120 0.0 -25 195 -75 50 0.1 mA mA mA mA k V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 27 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic TIMING (REF TO FIG 7) TXD Dominant State Timeout Bus dominant clamping detection Propagation loop delay TXD to RXD, recessive to dominant Propagation delay TXD to CAN, recessive to dominant Propagation delay CAN to RXD, recessive to dominant Propagation loop delay TXD to RXD, dominant to recessive Propagation delay TXD to CAN, dominant to recessive Propagation delay CAN to RXD, dominant to recessive Loop time TXD to RXD, Slew rate 1 (Selected by P_SPI) Rec to Dom Dom to Rec Loop time TXD to RXD, Slew rate 2 (Selected by P_SPI) Rec to Dom Dom to Rec STATE MACHINE TIMING External Wake-up Filter Time 3-Pulse pattern wake-up - Pulse width VDIFF = 1.15 V, Ta =-40C VDIFF = 2.0 V, Ta =-40C VDIFF = 1.15 V, 25C Ta 125C. Time to report local wake-up event Time to report CAN wake-up event Device state transition time (P_SPI versus static mode change distinction) except from Standby and Go To Sleep modes Transition time from Standby mode to any mode Transition time from go to sleep to Sleep mode (Go To Sleep command) VIO low to Sleep mode timing VDD low to CAN driver disable timing VDD low to regulator disable timing PSEUDO SPI (P_SPI)TIMING P_SPI Operation frequency SCLK Clock High Time SCLK Clock Low Time EN to Falling Edge of STBY Falling Edge of STBY to EN ERR rise Time CL = 15 pF ERR fall Time CL = 15 pF tFSO 25 50 ns FREQ tWSCLKH tWSCLKL tSISU tSIH tRSO 0.0625 0.125 0.125 40 40 25 4.0 8.0 8.0 50 MHz s s ns ns ns tLOC WAKEREP
Symbol
Min
Typ
Max
Unit
tDOUT tDOM tLRD tTRD tRRD tLDR tTDR tRDR tLOOPSL1
300 300 60 50 50
600 700 140 70 45 120 75 50 -
900 1000 210 110 140 200 150 140 310
s s ns ns ns ns ns ns ns
tLOOPSL2
50
-
310
ns
tWAKE tPWIDTH
2.5 2.0 2.0 8.0 -
10 35 25 35 35 10 10 50
15 -
s s
s s s s s ms ms ms
tCAN WAKEREP
tDEV-TR tLP-NP tH tVIO- SLP tVDD-CANOFF tVDDOFF
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 27 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Time from Rising Edge of STBY to ERR valid data Delay Between P_SPI Command and CAN in Normal Mode or CAN in Sleep mode. Device in Normal mode (measured after P_SPI 8th clock cycle rising edge). Symbol tVALID tCANON-OFF Min Typ Max 50 20 Unit ns s
TIMING DIAGRAMS
tPCLK tWSCLKH tWSCLKL
STBY
D7
Dn
tSIH tSISU
D0
EN
tVALID
Di7
Din
Di0
ERR
Do7
Do6
Do0
EN and ERR state changed at STBY rising edge
Figure 4. P_SPI Timing
TXD 0.3 VIO RXD
tLRD 0.7 VIO tLDR 0.3 VIO 0.7 VIO
Figure 5. Propagation Loop Delay TXD to RXD
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TXD 0.3 VIO VDIFF
tTRD 0.7 VIO tTDR 0.9 V tRRD 0.5V tRDR 0.7 VIO
RXD
0.3 VIO
Figure 6. Propagation Delays TXD to CAN and CAN to RXD
12 V 10 F 5.0 V 100 nF 5.0 V EN STBY Signal generator TXD RXD 15 pF CANL GND SPLIT All pins are not shown VSUP VIO VDD 100 nF 2.2 F
33902
CANH
RBUS 60
CBUS 100 pF
Figure 7. Test Circuit for Timing Characteristics
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION TRANSMIT DATA (TXD)
This input is the CAN transmit data pin. It is the interface from the MCU to the output on the CAN bus. If TxD is low (dominant), then the signal on the CAN bus will be dominant (CANH is ~5.0 V and CANL is ~0 V). If TxD is high (recessive), then the signal on the CAN bus will be recessive (CANH and CANL will be ~2.5 V). The TxD thresholds are 3.3 V and 5.0 V compatible (depending on VIO voltage) to accommodate the implementation of various MCUs. There are three slew rates available, which are selected via the Pseudo SPI. is expected to shut down, which would then turn off the MCU and any other device that is powered up by the external regulator. This should considerably decrease the module's current consumption.
ACTIVE LOW ERROR (ERR)
The dedicated active low flag reporting pin reports any static errors, flags and wake-ups to the MCU depending on devices operating state. MISO (Master In, Slave Out) during Pseudo SPI communication.
GROUND (GND)
Ground termination pin.
WAKE (WAKE)
The Wake input pin is used to wake-up the device from sleep mode after a Battery to Gnd, or Gnd to Battery transition. This pin is usually connected to an external switch in the application module, and SHOULD NOT be left open. If Wake pin functionality is not being used, it should be connected to GND to avoid false wake-ups. This pin exhibits a high-impedance for low input current when implemented below 18 V. If voltage exceeds 18V at the pin, a series resistor should be used to limit the amount of current that the device will start sinking.
VOLTAGE DIGITAL DRAIN (VDD)
This is the dedicated embedded supply voltage for the CAN interface. A capacitor must be connected to this pin. CAN interface current is sourced from this pin if device is in transmit and receive mode. In low power modes, current for the CAN interface is sourced directly from the VSUP pin.
RECEIVE DATA (RXD)
This output pin is the CAN receive data. It is the interface to the MCU, which reports the state of the CAN bus. If the CAN bus is recessive (CANH and CANL ~2.5 V), then the signal on RxD will be high (recessive). If the CAN bus is dominant (CANH is ~5.0 V and CANL is ~0 V), then the signal on RxD will be low (dominant). This pin is also an active-low wake-up flag in low power, which reports a wakeup event to the MCU. RxD thresholds are 3.3 V and 5.0 V compatible (depending on the VIO voltage) to accommodate the implementation of various MCUs.
VOLTAGE SUPPLY (VSUP)
This is the power supply input pin. The DC operating voltage for the device is 5.5 V to 27 V. A reverse battery protection diode should be implemented. This pin is able to sustain automotive transient conditions, such as 40 V load dumps and 27 V jump start conditions. The device's quiescent sleep current is typically around 10 A.
SPLIT (SPLIT)
This is the output pin for middle point connection of CANH and CANL when implementing split termination. Pin voltage is typically around half of VDD (2.5 V) with or without loads. This pin must be left open if split CAN termination is not implemented.
VOLTAGE SUPPLY FOR I/O (VIO)
This is the dedicated input supply pin to determine voltage thresholds for the digital input/output pins. The VIO thresholds range from 2.75 V to 5.5 V to accommodate the implementation of 3.3 V or 5.0 V MCUs.
ENABLE (EN)
This is the enable input pin for device static mode control. This pin is connected to the MCU to place transceiver in the desired mode. Functional voltage thresholds are determined by VIO voltage to accommodate the implementation of 3.3 V or 5.0 V MCUs. MOSI (Master Out, Slave In) during Pseudo SPI communication.
CAN HIGH (CANH)
This is the CAN High input/output pin. CANH circuitry is design to work as a high side switch connected to VDD. In the recessive state, this switch is turned off and CANH is then biased to SPLIT voltage or GND, depending on device's operating state. In the dominant state, the switch is turned on and CANH is biased to VDD voltage. The CANH pin is protected and diagnostics reporting is available against short to Battery, Gnd, and 5.0 V (VDD).
INHIBIT (INH)
The inhibit output pin controls an external power supply regulator. When the INH output is low, the external regulator
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
CAN LOW (CANL)
This is the CAN Low input/output pin. CANL circuitry is design to work as a low side switch connected to GND. In the recessive state, this switch is turned off and CANL is then biased to SPLIT voltage or Gnd, depending on device's operating state. In the dominant state, the switch is turned on and CANL is biased to GND voltage. The CANL pin is protected and diagnostics reporting is available against short to Battery, Gnd, and 5.0 V (VDD).
STANDBY (STBY)
This is the standby input pin for device static mode control. This pin is connected to the MCU to place transceiver in the desired mode. Functional voltage thresholds are determined by VIO voltage to accommodate the implementation of 3.3 V or 5.0 V MCUs. CLK (Clock) during Pseudo SPI communication.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES STATE DIAGRAMS
STBY 1 EN 1 and VIO > VIO low threshold
if VIO ON (2)
Normal mode (STBY 1, EN 1)
VDD ON, INH ON
STBYB 1 EN 1
STBYB 0 EN 1
Go to sleep (STBY 0, EN 1)
VDD ON, INH ON
(From any state if VI/O low, after
Driver ON; Receiver ON, SPLIT 2.5 V ERR report: wake-up source & (VDD low and CAN bus failure) (7)
STBY 1 EN 1 STBY 1 EN 1
Terminated to ground, SPLIT HZ ERR report: Wake-up
STBY 0 EN 1 STBY 0 EN 1
TVIO-SLP, if VSUP > VSUV
t>tH
Sleep (STBY 0, EN 0)
Automatic transition Controlled transition
(4 )
(4)
VDD OFF, INH HZ (6)
Terminated to ground, SPLIT HZ ERR report: Wake-up (2) Local or CAN wake-up
STBY 1 EN 0
STBY 1 EN 0
STBY 0 EN 0
Listen Only (STBY 1, EN 0)
VDD ON, INH ON
Standby (STBY 0, EN 0)
STBY 1 EN 0 STBY 0 EN 0
Driver OFF; Receiver ON, SPLIT 2.5 V ERR report: BATfail) (1)
(VDD low, local failure) (3)
VDD ON (5), INH ON
Terminated to ground, SPLIT HZ ERR report: Wake-up
Power up
Legend:
Mode (STBY, EN)
(VDD ON, INH) (CAN, SPLIT) (ERR)
STBY 1 EN 0 and with VIO > VIO low threshold
Power Down
if VIO ON (2)
Notes 1. Coming from Standby mode 2. If VI/O is still switched on 3. 4. 5. 6. 7. Coming from Normal mode If batfail flag and wake-up flag are cleared. An attempt to enter Sleep mode without batfail and wake-up flag cleared has no effect Limited current capability, to maintain the capacitor at VDD charged. A high level on INH will report a wake-up in Sleep mode After 4 TXD pulses rising edge
Figure 8. State Diagram
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 5. Functional Table
STBY 0 0 0 1 1 EN 0 0 1 0 1 Mode Standby Sleep Go to sleep Listen Only Normal VDD ON
(8)
INH High HZ High High High
RXD Active LOW: report wake-up event (9)
CAN Terminated to GND Receiver: ON Driver: OFF Driver and Receiver: ON
ERR (active low) Active LOW: report wake-up event (9) *Report local failure, VDD low, Bat fail *wake-up source (10) *BUS failures, VDD low
OFF ON ON ON
High: recessive state Low: dominant state
Notes 8. With limited current capability, in order to maintain the capacitor at VDD pin charged 9. 10.
VSUP VSUP_low 5.8 V VSUP_low 5.0 V ~3.0 V VDD 5.0 V 4.25 V 4.25 V 5.8 V VDD CAN driver enabled 5.0 V 4.25 V
Provided if VIO > 2.5 V. Before 4th TX pulse rising edge
Start VDD overload condition VDD re-enabled 4.25 V
End
VDD_low
VDD_low
50 ms (3) 10 ms VDD re-enabled (2) 50 ms 10 ms CAN driver disabled ERR(1) EN, STBY, VIO high VDD disabled (3) ERR(1) MODE
VDD disabled
CAN driver disable
Normal or Listen Only
Normal or Listen Only
2 VDD low illustration, VSUP > VSUP low (VSUP > 5.8 V)
VDD low illustration, cranking pulse VSUP < VSUP low (VSUP < 5.8 V) and CRANK bit low in P_SPI register. 1) See figure on ERR reporting 2) VDD is re enabled when VSUP recovers (VSUP low flag goes from H to L) or by a mode change via EN and STBY input. 3) Capacitor charged maintained by internal device current source
Figure 9. VDD Low Illustration
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
DEVICE STATE DESCRIPTION
STANDBY MODE Standby mode is a reduced current consumption mode. CANH and CANL lines are terminated to GND, the SPLIT pin is high-impedance. In order to monitor bus activities, the CAN wake-up receiver is ON, INH output remains ON. The voltage on VIO should be maintained. The VDD regulator is ON with limited current capability, in order to maintain the capacitor at VDD charged and allow a fast transition to Normal mode and fast CAN communication. Wake-up events occurring on the CAN bus or on the WAKE pin are reported by a low level of the ERR and RXD pins. The Standby mode is also the first mode entered after a device power up. In this case, the VDD regulator is activated to charge the VDD capacitor, and then the regulator enters the reduced current capability mode, in order to optimize and reduce system current consumption. Depending upon the VDD capacitor `s Equivalent Series Resistance (ESR), a voltage drop can be observed. See Figure 10.
LISTEN ONLY MODE This mode is used to disable the CAN driver, but leave the CAN receiver active. In this mode, the device is only able to report the CAN state on the RXD pin. The TXD pin has no effect on CAN bus lines. This mode is entered by setting the EN and STBY pins to [0, 1]. In this mode, coming from Normal mode, the ERR pin reports local failures occurring on the TXD and RXD pins, and VDD low. When this mode is entered from the Standby mode, the ERR pin reports the BATFAIL flag. The VDD regulator is ON. The SPLIT pin is active and a 2.5 V biasing is provided on the SPLIT output pin. GO TO SLEEP MODE Go to sleep is an intermediate mode to ultimately set the device in Sleep mode. The go to sleep is entered by setting the EN and STBY pins to [1, 0]. If the EN and STBY pins are maintained to [1,0] for a time longer than tH, the Sleep mode is automatically entered. In go to Sleep mode, the VDD regulator remains in its previous state and the SPLIT pin is deactivated. INH is active. SLEEP MODE The Sleep mode is a low power mode. It is entered from the Go To Sleep mode by setting the EN and STBY pins to [1 0], and automatically from Go To Sleep mode after tH. In Sleep mode, the VDD regulator is turned off and the SPLIT pin is deactivated, INH is high-impedance. In Sleep mode and Go To Sleep mode, the device is able to wake-up on CAN bus activity or transitions on the WAKE pin. A wake-up from Sleep mode will set the device in Standby mode. Sleep mode is also automatically reached if the voltage at VIO is below the VIOTH for more time than TVIO-SLP.
5V VDD low (4.25 V) device start-up VE VE
VE 0V EN, STBY
VE = esr x VDD current limitation
Main VDD ON wake-up event detected
Main regulator OFF Weak regulator ON
Main VDD ON
DEVICE MAIN FLAGS DESCRIPTION:
Sleep Standby Normal
Figure 10. VDD Regulator Start-up NORMAL MODE In Normal mode, both the CAN driver and receiver are ON. In this mode, the CAN bus is controlled by the TXD pin level, and the CAN bus state is reported on the RXD pin. The VDD regulator is ON. It supplies the CAN driver and receiver.The SPLIT pin is active and a 2.5 V biasing is provided on the SPLIT output pin. In Normal mode, the ERR pin reports the wake-up source and the bus failure, after 4 TXD pulses. Normal mode is entered by setting the EN and STBY pins high. Entering Normal mode will clear the BATFAIL flag.
This section describes the flags available when the device is controlled via the EN and STBY pins in a static manner (no P_SPI control). Additional information and control are possible using the Pseudo SPI (refer to Extended device operation). BATFAIL This flag is set to signal that the voltage on the VSUP pin has dropped below VBFTHS, particularly after the device was disconnected from the battery. In Listen Only mode, the BATFAIL flag will be available on the ERR pin, coming from standby, Go To Sleep and Sleep modes. When VSUP is below VBF threshold, all internal flags and registers are reset to their initial condition. CAN Bus Wake-up (WU) From Standby or Sleep mode, this flag is set if a correct pattern has been received on the CAN bus. This wake-up is reported on ERR and RXD pins by a low level in Standby mode, as well as in Sleep mode if VIO is present.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
The flag is cleared by leaving the Normal mode or by a P_SPI reading. WAKE Pin - Local Wake-up (WU) From the Standby, Go To Sleep or Sleep mode, this flag is set if a transition on the WAKE pin is detected. This wake-up is reported on the ERR pin by a low level in Standby mode, as well as in Sleep mode if VIO is present. The wake-up flag is cleared by leaving the Normal mode or by P_SPI reading. Wake-up Source Wake-up source is reported on the ERR pin by entering Normal mode, before 4 TX pulses. The ERR pin is low to indicate a local wake-up, and high to indicate CAN wake-up. Local Failure This flag is a logic OR of the following failures: TXD dominant clamping, RXD recessive clamping, TXD-to-RXD short-circuit and VDD low condition. This flag is reported in Listen Only on the ERR pin coming from Normal mode. Using the P_SPI, it is possible to get detailed failure information. BUS Failure The BUS failure flag is set if the CAN transceiver detects a bus line short-circuit condition to VSUP, VDD, or GND, during five consecutive dominant-recessive cycles on the TXD pin. In addition, this flag reports a bus dominant clamping condition. In Normal mode, the bus failure flag is available on the ERR pin.
Using the P_SPI, it is possible to get detailed failure information. VDD low VDD low flag is set in Normal and Listen Only mode when VDD is below the VDD low threshold. After a time longer than tVDD-CANOFF, the CAN is disabled and after a time longer than tVDDOFF, the VDD regulator is disabled to avoid a battery discharge. If the CRANK bit is set high, the VDD regulator and CAN will not be disabled if VSUP is below VSUV. When VSUP is above VSUV, the CRANK bit has no effect. VDD low flag is reported in Normal and Listen Only mode, so the user can differentiate between local and bus failures by changing modes and observing ERR staying low. In case of a double failure (local and bus failure) at the same time, the results will be the same: ERR low in Normal and in Listen Only mode. However, this is unlikely to occur. This flag is cleared when entering low power, or when VDD is above VDD low threshold, plus the P_SPI reading. The VDD regulator is re enabled as soon as VSUP rises above VSUP low, or by a mode change (refer to the crank pulse illustration). The CAN is re-enabled as soon as VDD is above VDD low threshold. (refer to crank pulse illustration). ERR Pin The ERR pin reports various information depending upon the device state, the device state transition, and event on the TXD pin. Table 6 shows the diagnostic flag availability when the device is controlled in a static manner.
Table 6. "Static" Diagnostic Flags Flag
BATFAIL CANWU or Local WU Wake-up source BUS Failure Local Failure VDD low Evaluation mode
Accessibility
Listen-Only mode (coming from Standby, Go-to-Sleep, Sleep) Standby, Go-to-Sleep, Sleep (provided VIO is present) Normal mode (Before the fourth dominant to recessive edge on the TXD pin) Normal mode (After the fourth dominant to recessive edge on the TXD pin) Listen Only mode (coming from Normal mode) Normal mode (After the fourth dominant to recessive edge on the TXD pin) and Listen Only mode (coming from Normal mode) By RXD low, when coming from Sleep or Standby into Normal or Listen Only modes.
Clearing Diagnostic
Leaving Normal mode Leaving Normal mode or by setting the BATFAIL Leaving Normal mode, or by setting BATFAIL flag. Re-entering Normal mode Entering Normal mode or TXD high while RXD low. VDD > VDD low threshold RXD goes from low to high, to signal the device is ready and has exited low power modes (TLP-NP parameter).
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Figure 11 shows the meaning of the ERR pin versus the device state, the state transition and the events on TXD. DEVICE MODE
WAKE-UP SOURCE Local Wake-up => ERR low; CAN Wake-up => ERR high
STBY = 1 EN = 1 STBY = 1 EN = 1 STBY = 1 EN = 1 STBY = 1 EN = 0 STBY = 1 EN = 0
ERR MEANING
4 dominant pulses at TXD BUS FAILURE, VDDlow, Bus dom, CANH or CANL short to GND 5.0 V or VBAT => ERR low
NORMAL
STBY = 1 EN = 1
LISTEN ONLY
STBY = 1 EN = 0
BATFAIL VSUP Low =>ERR high
STBY = 1 EN = 0
LOCAL FAILURE VDD low, TXD-PD, RXD-PR, TXD short to RXD => ERR low
GO TO SLEEP STANDBY SLEEP
STBY = 0 EN = X
STBY = 0 EN = X
STBY = 0 EN = X
STBY = 0 EN = X
STBY = 0 EN = X
WAKE-UP EVENT CAN Wake-up or Local Wake-up => ERR low
Figure 11. ERR versus device state
CAN INTERFACE DESCRIPTION:
CAN Interface Supply The supply voltage for the CAN driver is the VDD pin. The CAN interface also has a supply path from the battery line, through the VSUP pin. This path is used in CAN Sleep mode to allow wake-up detection. During CAN communication (transmission and reception), the CAN interface current is sourced from the VDD pin. During CAN low power mode, the current is sourced from the VSUP pin. CAN Driver Operation in Normal Mode The CAN driver will be enabled as soon as the device is in Normal mode and the TXD pin is recessive. When the CAN interface is in Normal mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD pin. The bus state is reported through the RXD pin. When TXD is high, the driver is set in the recessive state, and CANH and CANL lines are biased to the voltage set at VDD divided by 2, approx. 2.5 V. When TXD is low, the bus is set into the dominant state, and the CANL and CANH drivers are active. CANL is pulled low and CANH is pulled high. The RXD pin reports the bus state: CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV).
If "CANH minus CANL" is below the threshold, the bus is recessive and RXD is set high. If "CANH minus CANL" is above the threshold, the bus is dominant and RXD is set low. The SPLIT pin is active and provide a 2.5 V biasing to the SPLIT output. Normal Mode and Slew Rate Selection The CAN signal slew rate selection is done via the P_SPI. By default, and if no P_SPI is used, the device is in the fastest slew rate. Three slew rates are available. The slew rate controls the recessive to dominant and dominant to recessive transitions, which are also dependent on CANH and CANL capacitance. This also affects the delay time from the TXD pin to the bus, and from the bus to RXD. The loop time is thus affected by the slew rate selection. Minimum Baud rate The minimum baud rate is determined by the shortest TXD permanent dominant timing detection. The maximum number of consecutive dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag). The shortest TXD dominant detection time of 300 s leads to a single bit time of: 300 s / 12 = 25 s. So the minimum Baud rate is 1 / 25 s = 40 kBaud.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Termination The device supports the two main types of bus terminations: * Differential termination resistors between CANH and CANL lines * Split termination concept, with the mid point of the differential termination connected to GND through a capacitor, and to the SPLIT pin * Refer to Typical Application and Bus Termination Options and WAKE Pin Configuration on page 27
.
TXD
Low Power Mode In low power mode, the CAN is internally supplied from the VSUP pin. In low power mode, the CANH and CANL drivers are disabled, and the receiver is also disabled. CANH and CANL have a typical 40 k impedance to GND. The wake-up receiver can be activated if wake-up is enabled by the P_SPI command. The SPLIT pin is high-impedance. When the device is set back into Normal mode, CANH and CANL are set back into the recessive level. This is illustrated in the following diagram.
Dominant state CANH-DOM
Recessive state
CANH 2.5 V CANL CANL-DOM RXD SPLIT 2.5 V MC33902: bus driver CANH-CANL
CANL/CANH-REC
High ohmic t termination (50kohms) to GND
MC33902: receiver (bus dominant set by other IC) Normal or Listen Only mode
High-impedance Go to Sleep, Sleep or Standby mode
Normal or Listen Only mode
Figure 12. Bus Signal in Normal and Low Power Mode Wake-up When the CAN interface is in Sleep mode with wake-up enabled, the CAN bus traffic is detected. The CAN bus wakeup signal is a pattern wake-up. CAN wake-up cannot be disabled. CAN Wake-up Report The CAN wake reports depend upon the low power mode selected, Sleep or Standby. In Sleep mode, the INH pin is activated. In Standby mode, the VIO voltage is present and the wake-up is reported by the ERR and RXD pin low level. Ref to Table 5.
.
CANH CAN bus Dominant Pulse # 1 CANL Dominant Pulse # 2 Dominant Pulse # 3 Dominant Pulse # 4
Pattern Wake-up In order to wake-up the CAN interface, the wake-up receiver must receive a series of 3 consecutive valid dominant pulses. This is the default setting in which the CAN WU-pattern bit is set low. CAN WU-pattern bit can be set high by P_SPI, and the wake up will occur after a single pulse duration of a minimum of 4.0 s. A valid dominant pulse should be longer than tPWIDTH. The 3 pulses should occur in a time frame of 120 s to be considered valid. When 3 pulses pass these criteria the wake signal is detected. This is illustrated in Figure 13.
Incoming CAN Message
Internal differential wake-up receiver signal Internal wake-up signal
min tPWIDTH
max 120 s
Figure 13. Pattern Wake-up
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
CAN BUS DIAGNOSTIC
The aim is to implement a diagnostic of bus short-circuit to GND, VBAT, and the internal application circuit board 5.0 V. Several comparators are implemented on the CANH and
H5 Hb TX Diag Hg Lg VR5
CANL lines. These comparators monitor the bus level in the recessive and dominant states. The information is then managed by the logic circuitry to properly determine the failure and report it.
VBAT (12-14 V) VRVB VDD CANH CANL VRVB (VSUP-2.0 V) VDD (5.0 V) VR5 (VDD-.43 V) CANH dominant level (3.6 V) Recessive level (2.5 V) VRG (1.75 V) CANL dominant level (1.4 V) GND (0.0 V)
VRG
Logic
VRG Lb L5 VRVB VR5
Figure 14. CAN Bus Simplified Structure Truth Table for Failure Detection Table 7 indicates the state of the comparators in case of a bus failure, and depending upon the driver state. Table 7. Failure Detection Truth Table
Failure description No failure CANL to GND CANH to GND No failure CANL to VBAT CANH to VBAT No failure CANL to 5.0 V CANH to 5.0 V Driver recessive state Lg (threshold 1.75 V) 1 0 0 Lb (threshold VSUP-2.0 V) 0 1 1 L5 (threshold VDD-0.43 V) 0 1 1 Hg (threshold 1.75 V) 1 0 0 Hb (threshold VSUP-2.0 V) 0 1 1 H5 (threshold VDD-0.43 V) 0 1 1 Driver dominant state Lg (threshold 1.75 V) 0 0 0 Lb (threshold VSUP-2.0 V) 0 1 0 L5 (threshold VDD-0.43 V) 0 1 0 Hg (threshold 1.75 V) 1 1 0 Hb (threshold VSUP-2.0 V) 0 1 1 H5 (threshold VDD-0.43 V) 0 1 1
Detection Principle In the recessive state, if one of the two bus lines are shorted to GND, VDD, or VBAT, the voltage at the other line follows the shorted line, due to the bus termination resistance. For example: if CANL is shorted to GND, the CANL voltage is zero, the CANH voltage measured by the Hg comparator is also close to zero. In the recessive state, the failure detection to GND or VBAT is possible. However, it is not possible with the above implementation to distinguish which of the CANL or CANH lines are shorted to GND or VBAT. A complete diagnostic is possible once the driver is turned on, and in the dominant state. Number of Samples for Proper Failure Detection The failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. The error will be fully detected after 5 cycles of the recessive-dominant states. As long as the failure detection
circuitry has not detected the same error for 5 recessivedominant cycles, the error is not reported. Bus clamping detection If the bus is detected to be in dominant for a time longer than (tDOM), the bus failure flag is set and the ERR is set low in Normal mode. Such conditions could occur if the CANH line is shorted to a high voltage. In this case, current will flow from the high voltage short-circuit through the bus termination resistors (60 ) and then in the Split terminal (if used), and through the device CANH and CANL input resistors, which are terminated to an internal 2.5 V biasing or to GND (Sleep mode). Depending upon the high voltage short-circuit, the number of nodes, usage of split terminal, RIN actual resistor, and node state (sleep or active), the voltage developed across the bus termination can be sufficient to create a positive dominant voltage between CANH and CANL. The RXD pin will be low. This would prevent the start of any CAN
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
communication, and thus a proper failure identification (requires 5 pulses on TXD). The bus dominant clamp circuit will help to determine such failure situation. RX Permanent Recessive Failure The aim of this detection is to diagnose an external hardware failure at the RX output pin and ensure that a
TXD Diag VIO/2 VIO RXD RX driver Diff CANL Rxsense VDD CANH 60 RXD output RX flag Prop delay Logic TX driver Diff output CANL&H
permanent failure at RX does not disturb the network communication. If RX is shorted to a logic high signal, the CAN protocol module within the MCU will not recognize any incoming message. In addition it will not be able to easily distinguish the bus idle state and can start communication at any time. In order to prevent this, an RX failure detection is necessary.
Sampling
Sampling RX short to VDD RX flag latched
The RX flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
Figure 15. RX Path Simplified Schematic, Rx Short to VDD Detection Implementation for Detection The proposed implementation is to sense the RXD output voltage at each low to high transition of the differential receiver. Excluding the internal propagation delay, the RXD output should be low when the differential receiver is low. In case of an external short to VDD at the RXD output, RXD will be tied to a high level and can be detected at the next low to high transition of the differential receiver. As soon as the RXD permanent recessive is detected, the RXD driver is deactivated. Once the error is detected, the flag is latched and the driver is disabled. The error is reported at ERR pin and via P_SPI. Recovery Condition The internal recovery is done by sampling a correct low level at the Bus as shown in Figure 16.
CANL&H
Diff output Sampling Rx short to VDD Rx no longer shorted to VDD Sampling
RXD output
Rx flag latched RX flag (internal signal)
Figure 16. RX Path Simplified Schematic, Rx Short to VDD Detection
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Important Information for Bus Driver Reactivation RXD The driver stays disabled until the failure is cleared (RX is no longer permanent recessive). One transition on the CAN bus (internal differential receiver transition), and the bus driver is activated by entering into Normal mode.
TXD PERMANENT DOMINANT
Principle If the TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible. The 33902 has a TXD permanent time out detector. After the timeout, the bus driver is disabled and the bus is released into a recessive state. The TXD permanent flag is set. Recovery The TXD permanent dominant is used and activated in case of a TXD short to RXD. The recovery condition for a TXD permanent dominant (recovery means the re-activation of the CAN drivers) is done by entering into a Normal mode controlled by the MCU, or when TXD is recessive, while RXD changes from recessive to dominant.
In read mode, the following flags are available: - CAN bus detail diagnostic - Local failure diagnostic - Voltage monitoring - Wake-up flags, wake pin level - P_SPI errors - Device identification P_SPI Diagram Figure 17 illustrates the P_SPI operation. A clock signal should be generated on the STBY pin, EN input operates as Data In (MOSI) and the ERR output pin operates as Data Out (MISO). In order to start a P_SPI operation, the level at STBY should be low (1), as shown in Figure 17. Bit D7 starts at the rising edge of STBY. Bit D7 level should be opposite to the level before. D7 is then internally sampled at the STBY falling edge. The sampling of opposite level at (1) and (3) is the confirmation of a P_SPI message start. Then the P_SPI bit D6 starts, and the device will drive the ERR pin to a level opposite to the one when P_SPI started (5): this is the confirmation that the device has correctly detected a P_SPI message start (acknowledgement).
TXD TO RXD SHORT CIRCUIT:
Principle If TXD is shorted to RXD during incoming dominant information, RXD is set low. Consequently, the TXD pin is low and drives CANH and CANL into a dominant state. Thus the bus is stuck in dominant state. No further communication is possible. Detection and Recovery The TXD permanent dominant time out will be activated and release the CANL and CANH drivers. However, at the next incoming dominant bit, the bus will then be stuck in dominant again. The recovery condition is same as the TXD dominant failure.
D7 (2) STBY (1) (3) EN EN EN (4)
D6
Adr Adr
Device in Normal mode EN=1 Device in Listen Only EN=0
EN P_SPI msg start
EXTENDED DEVICE OPERATION
The device has extended functionality which allows device control and diagnostic readings via the P_SPI (Pseudo Serial Peripheral Interface), and using the STBY, EN and ERR pins. ERR P_SPI Operation The P_SPI operation is similar to a standard SPI interface operation in slave mode. It uses the EN, STBY and ERR pins, which have the functions of MOSI, SCLK and MISO. There is no chip select (CS). In write mode, the following functions and control are accessible: - CAN driver slew rate selection - ERR pin operation mode - CAN wake-up mode - CRANK mode operation ERR
ERR (5) ERR
ERR pin high at P_SPI start ERR pin low at P_SPI start
P_SPI msg detected (=acknowledge) Figure 17. : P_SPI Message Start Full P_SPI Message: Figure 4 describes the complete P_SPI message and timing.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Distinction Between P_SPI and Traditional Operation. The distinction between static device control and control via P_SPI is performed by the duration of the EN and STBY level. If the EN and STBY levels change before a time of "tDEV-TR" then the device detects a P_SPI operation. If the EN and / or STBY levels are stable for a time longer than 15 s, then the device state will be changed according to EN / STBY level and device state diagram. This means that the device mode change is done after a delay of typ tDEV-TR and consequently the P_SPI frequency operation should be faster than (1 / (2 * tDEV-TR). With tDEV-TR = 8.0 s, the SPI equivalent frequency should be greater than 62.5 kHz. End of P_SPI Message: At the P_SPI message, the state of EN and STBY pins should be in line with the device mode expectation: example: Table 8. P_SPI Bit Mapping
D7 MOSI MISO MOSI MISO MOSI MISO MOSI MISO STAR T ERR STAR T ERR STAR T ERR STAR T ERR D6 ADRR ACK=ER Rb 0 ACK=ER Rb 0 ACK=ER Rb 1 ACK=ER Rb 0 Bus dom D5 Rb/W MISO 5 0 (read) 0 1 (write) 0 1 VDD temp 0 0 BATFA IL D4 MOSI 4 MISO 4 1 X
If the device is in Normal mode and should stay in Normal mode after the P_SPI command, the EN and STBY pins should be 1,1 at end of the P_SPI command. If the device is in Listen Only mode, EN and STBY pins should be 0,1, in order to set or maintain the device in Listen Only mode. Time between 2 P_SPI Message: A min delay of 15 s should be observed between two P_SPI messages. The delay is measured between the last transition of the EN/STBY of the 1st message, and the 1st EN/STBY transition of the next message. P_SPI Availability: The P_SPI is operating only in Normal and Listen Only mode. It is not operating in Standby and Sleep modes. Table 8 is the mapping of the P_SPI register.
D3 MOSI 3 MISO 3 0 1
D2 MOSI 2 MISO 2 0 1 Test/ def 0
D1 MOSI 1 MISO 1 1 0 CANF
D0 MOSI 0 MISO 0 1 0
LxWU WILS CANW U CAN SR1 PASS ID1
VMONF SPIerr CAN WU - pattern MET ID1 0 1
ERR_EXT
0 1
CAN SR0 PASS ID0 0 1
CRANK MET ID0 0 1
0
1
Rx-PR CAN cur Tx-PD
VSO CANF2 VSUV CANF1 VIO low CANF0 VDDlo V w
Low power mode definition: Standby, Go To Sleep and Sleep modes.
Description Set BATFAIL Reset Action
VSUP voltage < VSUP low threshold, also called Power On flag VSUP below VBFTH (3.3 V) Entering Normal mode or P_SPI reading (Listen Only) Avoid entering Go To Sleep. Set ERR low in Listen Only mode coming from low power modes
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Description Set LxWU Reset Action Description Set CANWU Reset Action Description Set VMONF Reset Action Description Set CANF Reset Action Description Set WILS Reset Action Description Set SPIerr Reset Action Description Configure
Wake-up event occurred on the WAKE pin In low power mode, by a local wake pin transition Exit Normal mode or P_SPI reading (Listen Only and Normal mode) Avoid entering Go To Sleep mode. Set ERR low in low power modes Wake-up event occurred on CAN bus In low power mode, by CAN wake-up Exit Normal mode or P_SPI reading (Listen Only and Normal mode) Avoid entering Go To Sleep mode. Set ERR and RXD low in low power modes Voltage monitoring flag: OR of VSOV, VSUV, VIO, VDDLOW, VDD prewarning Temp In normal and listen only modes: OR of VSOV, VSUV, VIO, VDDLOW, VDD prewarning Temp Entering low power mode or (Failure removed + P_SPI reading (Listen Only and Normal mode)) If ERR_EXT is set, ERR pin set low. ERR is low for the VDD low flag, despite the ERR-EXT bit. Failure on the CAN bus. OR of CANF2, CANF1, CANF0 bits In Normal and Listen Only modes: OR of TXDPD, RXDPR, CANcur, CAN bus failures Entering low power mode or (Failure removed + P_SPI reading (Listen Only and Normal mode)) Depending upon failure. ref to detail flag description Real time WAKE input level. Low is WAKE below threshold, high is WAKE above threshold. WAKE pin higher than threshold WAKE pin lower than threshold No action Pseudo SPI error: Incomplete transmission error during start of P_SPI When P_SPI frame does not have 8 clock pulses Entering low power mode or P_SPI reading (Listen Only and Normal mode) P_SPI wrong command is ignored
ERR pin operation report all flags
By P_SPI Entering low power mode When high, extend the ERR output pin to report all flags (when available) in any modes. When low (default) ERR reports default flags.
ERR_EXT
Reset Action
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Description
00: CAN slew rate 0 11: CAN slew rate 0 01: CAN slew rate 1 10: CAN slew rate 2
CANSR (1,0)
Configure Reset Action Description Configure
By P_SPI in Listen Only and Normal mode Entering low power mode Change CAN slew rate (ref to parametric). Default is 00. Select between 2 wake-up mechanisms By P_SPI in Listen Only and Normal mode Leaving low power mode When high wake-up occurs after 1 pulse of a minimum of 4.0 s (parameter). When low, (default) wakeup occurs after 3 pulses of a minimum of 600ns (parameters). When this flag is set, the VDD low condition does not disable CAN and VDD regulator, if VSUV flag is set. By P_SPI in Normal and Listen Only modes Entering low power mode or P_SPI write (Listen Only and Normal mode) No disable of CAN and VDD regulator in case of a VDD low condition, and the VSUV flag is set. ERR reports a VDD low condition. The P_SPI VDD low flag is set. Report device internal identification
CAN WU pattern
Reset Action
Description Configure CRANK Reset Action
Set PASS ID(1,0), METID(1,0) Reset Action Description Set BUS dom Reset Action Description Set CAN cur Reset
Detect a bus voltage dominant for a time longer than tDOM. This flag is set if the bus is detected to be in dominant for more than tDOM Entering low power mode, bus recessive P_SPI reading (Listen Only and Normal mode) No action, set ERR low in Normal mode Over-current occurred on the CANH or CANL driver In Normal mode, if the CANH or CANL current exceed the threshold (parameter) Entering low power mode, the CAN current below threshold + P_SPI reading (Listen Only and Normal mode) By default no action. If the ERR-EXT bit is set, the ERR is set low.
Action
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Description Set RX-PR Reset
RXD short to high (recessive level) In Normal and Listen Only modes, if the RXD permanent recessive condition is detected Entering low power mode, the RXD recovery condition reached + P_SPI reading (Listen Only and Normal mode) Set the local failure flag, disable the CAN driver, set ERR low in Listen Only mode coming from Normal mode TXD permanent dominant In NORMAL modes, if TXD permanent dominant condition detected Entering low power mode, TXD recovery condition reached + P_SPI reading (Listen Only and Normal mode) Set the local failure flag, disable the CAN driver, set ERR low in Listen Only mode coming from Normal mode 0 0 0: No CAN bus failure 0 0 1:CANL short to GND 0 1 0: CANL short to VDD 0 1 1: CANL short to VBAT 1 0 1: CANH short to GND 1 1 0: CANH short to VDD
Action
Description Set TX-PD Reset
Action
Description
CANF (2,1,0) Set Reset
1 1 1: CANH short to VSUP In Normal modes, if CAN failure condition detected Entering low power mode, CAN failure recovery condition reached + P_SPI reading (Listen Only and Normal mode) Set the bus failure flag, set the ERR low in Normal mode after 4 Tx pulses VDD regulator reaches temperature prewarning In Normal mode or Listen Only mode, if the VDD temperature reaches the prewarning threshold Real time report, reset if the temperature falls below the prewarning threshold By default no action. If the ERR-EXT bit is set, ERR is set low. VSUP over-voltage detected In Normal and Listen Only modes, if the VSUP over-voltage threshold condition detected Entering low power mode, VSUP over-voltage threshold condition recovered + P_SPI reading (Listen Only and Normal mode) By default no action. If the ERR-EXT bit is set, the ERR is set low.
Action Description Set VDD temp Reset Action Description Set VSOV Reset
Action
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Description Set VSUV Reset
VSUP under-voltage detected In Normal and Listen Only modes, if the VSUP under-voltage threshold condition detected Entering low power mode, VSUP under-voltage threshold condition recovered + P_SPI reading (Listen Only and Normal mode) When VSUP voltage rises above the VSUS threshold, the VDD regulator is re-enabled if disabled previously by a VDD low condition VIO low detected In all modes, if VIO under-voltage threshold condition detected Entering low power mode, VIO under-voltage threshold condition recovered + P_SPI reading (listen only and normal mode) After 10ms, set the device in Sleep mode, if VSUV low (don't enter Sleep mode during crank and power up phase). VDD voltage < VDDLOW flag threshold In all modes, if VDD under-voltage threshold condition detected Entering low power mode, VDD under-voltage threshold condition recovered + P_SPI reading (Listen Only and Normal mode), mode change between Normal and Listen Only if VDD regulator was turned off previously by a VDD low condition for more than 50ms. After 10 ms, disable the CAN, after 50 ms disable the regulator, if CRANK bit is set low (default).
Action
Description Set VIO low Reset
Action
Description Set VDD low Reset
Action
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Typical application
D1
VBAT Rb S component list: D1: 1N4004 type C1: >=100 nF C2: >=100 nF C3: >=2.2 F C4: >=50 pF C5:>=50 pF C6: 1.0 to 10 nF C7: 1.0 to 63 F R1: 22 k Rb: customer defined, ex 10 k
VBAT
C7 C1
VSUP WAKE C4 INH VDD VIO EN C3
R1
VIN GND VREG VOUT
C2
EN
2.75 V to 5.0 V
VCC
MC33902
CANH 30 SPLIT 30 GND CANL C5 C6 C4 CAN bus
Micro controller
GPIO
STBY ERR
CAN Tx Protocol Controller Rx
TXD RXD
Supported CAN terminations
Split termination CANH 30 SPLIT 30 CANL C5 ECU connector C6 Standard termination CANH CANH No termination
C4 CAN bus
C4 No connect 60 CAN bus
C4 No connect CAN bus
SPLIT
SPLIT
CANL C5
CANL C5
MC33902: WAKE Pin Configurations
Switch to GND VBAT Rb WAKE S C4 Rb Switch to VBAT VBAT S R1 Unused WAKE WAKE
R1 WAKE C4
Figure 18. Typical Application and Bus Termination Options and WAKE Pin Configuration
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Analog Integrated Circuit Device Data Freescale Semiconductor
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COMPARISON WITH COMPETITION 14 PIN HIGH SPEED CAN TRANSCEIVER
COMPARISON WITH COMPETITION 14 PIN HIGH SPEED CAN TRANSCEIVER
The table below is a comparison between the MC33902 and the competition 14 pin high speed CAN transceiver having no embedded power supply.
Item VDD pin Wake pin MC33902 Output. Requires local decoupling capacitor(s). No extra load should be connected. Fixed threshold typ 3.0 V with hysteresis. No pull-up or pull-down. High-impedance input. Connect to GND when not used. Active low, reports flags, or used as MISO during P_SPI communication. Strong driver (capability typ. 3.0 mA). Competition w/o Embedded Regulator Input. Requires connection to a 5.0 V supply. Threshold VBAT -3.0 V. Active pull-up when input is above threshold. Active pull-down when input is below threshold. Active low, reports flags, weak driver, requiring 8.0 s stabilization time Input used for mode control.
ERR pin
EN and STBY pins Input used for static mode control. Used as CLOCK and MOSI during P_SPI communication. Bus dom failure flag VDD low flag
Failure reported on ERR pin in Normal mode Failure reported on the ERR pin in Listen Only mode (considered as a bus failure => reported in Normal mode) (considered as a local failure) No effect on device mode. Failure on CAN transceiver supply should not affect the complete ECU. VDD is disabled "locally" to reduce current consumption. The ERR pin is set low in Normal and Listen Only mode. VDD low threshold set at 4.25 V Same From Sleep or Standby mode, device needs 35 s typ. to be ready. At least 8.0 s, to differentiate between a static transition and P_SPI communication Set the device into Sleep mode. INH is turned OFF. If the ECU regulator is controlled by INH, ECU is turned OFF.
VIO low flag Wake-up time Transition time
Same No need for a delay for device ready. Immediate transition. However, the ERR pin has weak driver and an 8.0 s stabilization time is required. When the device is switched between Normal and Listen Only mode to check the fail flag, a delay of 8.0 s is needed.
33902
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ASB42565B listed below.
EF-PIN (PB-FREE) 98ASB42565B ISSUE H
33902
Analog Integrated Circuit Device Data Freescale Semiconductor
29
REVISION HISTORY
REVISION HISTORY
REVISION 3.0
DATE 8/2009
DESCRIPTION OF CHANGES
* Initial Release
33902
30
Analog Integrated Circuit Device Data Freescale Semiconductor
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MC33902 Rev. 3.0 8/2009

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